MCQ For BSNL TTA Paper II :Digital Techniques

MCQ For BSNL TTA Paper II :

Digital Techniques

The NAND gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: D
What is the binary equivalent of the decimal number 368
(A) 101110000 (B) 110110000
(C) 111010000 (D) 111100000
Ans: A
The decimal equivalent of hex number 1A53 is
(A) 6793 (B) 6739
(C) 6973 (D) 6379
Ans: B
The number of control lines for a 8 – to – 1 multiplexer is
(A) 2 (B) 3
(C) 4 (D) 5
Ans: B
The number of control lines for an 8 to 1 Multiplexer is 3
(The control signals are used to steer any one of the 8 inputs to the output)
How many Flip-Flops are required for mod–16 counter?
(A) 5 (B) 6
(C) 3 (D) 4
Ans: D
The number of flip-flops is required for Mod-16 Counter is 4.
EPROM contents can be erased by exposing it to
(A) Ultraviolet rays. (B) Infrared rays.
(C) Burst of microwaves. (D) Intense heat radiations.
Ans: A
EPROM contents can be erased by exposing it to Ultraviolet rays
(The Ultraviolet light passes through a window in the IC package to the EPROM chip
where it releases stored charges. Thus the stored contents are erased).
The digital logic family which has minimum power dissipation is
(A) TTL (B) RTL
(C) DTL (D) CMOS
Ans: D
The digital logic family which has minimum power dissipation is CMOS.
(CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip
area)
Data can be changed from special code to temporal code by using
(A) Shift registers (B) counters
(C) Combinational circuits (D) A/D converters.
Ans: A
Data can be changed from special code to temporal code by using Shift Registers.
(A Register in which data gets shifted towards left or right when clock pulses are
applied is known as a Shift Register.)
A ring counter consisting of five Flip-Flops will have
(A) 5 states (B) 10 states
(C) 32 states (D) Infinite states.
Ans: A
A ring counter consisting of Five Flip-Flops will have 5 states.
The speed of conversion is maximum in
(A) Successive-approximation A/D converter.
(B) Parallel-comparative A/D converter.
(C) Counter ramp A/D converter.
(D) Dual-slope A/D converter.
Ans: B
The speed of conversion is maximum in Parallel-comparator A/D converter
(Speed of conversion is maximum because the comparisons of the input voltage are
carried out simultaneously.)
The correction to be applied in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
Ans: B
The correction to be applied in decimal adder to the generated sum is 00110.
When the four bit sum is more than 9 then the sum is invalid. In such cases, add +6(i.e.
0110) to the four bit sum to skip the six invalid states. If a carry is generated when adding 6,
add the carry to the next four bit group .
The code where all successive numbers differ from their preceding number by single bit is
(A) Binary code. (B) BCD.
(C) Excess – 3. (D) Gray.
Ans: D
The code where all successive numbers differ from their preceding number by single bit
is Gray Code.
(It is an unweighted code. The most important characteristic of this code is that only a
single bit change occurs when going from one code number to next.)
Which of the following is the fastest logic
(A) TTL (B) ECL
(C) CMOS (D) LSI
Ans: B
ECL is the fastest logic family of all logic families.
(High speeds are possible in ECL because the transistors are used in difference
amplifier configuration, in which they are never driven into saturation and thereby the
storage time is eliminated.
Which of the memory is volatile memory
(A) ROM (B) RAM
(C) PROM (D) EEPROM
Ans: B
RAM is a volatile memory
(Volatile memory means the contents of the RAM get erased as soon as the power
goes off.)
-8 is equal to signed binary number
(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000
Ans: A
– 8 is equal to signed binary number 10001000
DeMorgan’s first theorem shows the equivalence of
(A) OR gate and Exclusive OR gate.
(B) NOR gate and Bubbled AND gate.
(C) NOR gate and NAND gate.
(D) NAND gate and NOT gate
Ans: B
The digital logic family which has the lowest propagation delay time is
(A) ECL (B) TTL
(C) CMOS (D) PMOS
Ans: A
The digital logic family which has the lowest propagation delay time is ECL
(Lowest propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into saturation and thereby
the storage time is eliminated).
The device which changes from serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP
Ans: C
The device which changes from serial data to parallel data is demultiplexer.
(A demultiplexer takes in data from one line and directs it to any of its N outputs
depending on the status of the select inputs.)
A device which converts BCD to Seven Segment is called
(A) Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer Ans: B
A device which converts BCD to Seven Segment is called DECODER.
(A decoder coverts binary words into alphanumeric characters.)
In a JK Flip-Flop, toggle means
(A) Set Q = 1 and Q(bar) = 0.
(B) Set Q = 0 and Q(bar) = 1.
(C) Change the output to the opposite state.
(D) No change in output.
Ans: C
In a JK Flip-Flop, toggle means Change the output to the opposite state.